Security and Fault Tolerance
William Robinson leads Vanderbilt's Security and Fault Tolerance Research group, whose mission is to conduct transformational research that addresses the reliability and security of computing systems.
Associate Professor of Electrical Engineering and Computer Engineering
Under recent NSF funding, William Robinson and collaborators are using the concept of information leakage to bridge the computer architecture and computer networking fields. An integrated, holistic approach can yield tremendous benefits in many areas such as network security and management and job scheduling in cluster grids.
This integration is a result of delay signatures in the network traffic that are composed of information leaked from internal components of a compute node (processor utilization). This information will be used to create completely new approaches to solve existing networking or architecture problems or to significantly improve the performance of existing approaches that address networking or architecture problems.
Using a hardware test bed, Robinson and researchers are investigating how various architectural components contribute to the delay signature. They hope to develop empirical and analytic models that will provide the framework to implement a general purpose engine that automates the process of using delay signatures. This engine would allow others to develop applications based upon the delay signature. The delay signature could also be used to increase the system's resiliency against degraded performance or failure.
The end goal is to provide extensive characterization and modeling of the behavior of the internal components of a node and the corresponding effect on network traffic generation. These results will enable researchers to address different aspects of node security/manageability and cluster grid scheduling.
In addition to this work, Robinson and his group address the threat of security vulnerabilities during the design and manufacture of integrated circuits (ICs) under both DARPA and the NSF Team for Research in Ubiquitous Secure Technology funding. The research would develop analysis techniques that can be used within traditional flows for electronic design automation to predict the risk associated with a particular IC.