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Simulation and testing for radiation effects at advanced technology nodes

Primary Investigators:
Bharat Bhuva
Brief Description of Project:
Our main research thrust is in the area of soft-error immune circuit design and single-event related simulations. The Student will need to design circuits that are immune to the single-event transient pulses generated when a heavy-ion traverses through an electronic transistor. The students must have excellent knowledge of digital  design and must be familiar with single-event effects. This project is aimed towards combinational logic and latch designs. Students will need to understand a little bit of CMOS layout and should be somewhat familiar with circuit simulations. Students will be required to carry out circuit-level simulations using Cadence tool suite.

Desired Qualification:
Junior/senior standing with digital circuit design and analysis experience.  Familiarity with CMOS layout is desired.  Strong self motivation, and the ability to work both independently and as part of a team are essential.

Nature of Supervision:
The student will interact with VU microelectronic circuits faculty and ISDE engineers in the analysis of radiation effects in advanced circuit designs.  The student will be assigned an RER graduate student as a day-to-day mentor.  Student will attend weekly technical research meetings with faculty, staff, graduate students, and other summer interns.

A Brief Research Plan (period is for 10 weeks):
Work with ISDE circuits faculty and engineers on a 10-week analysis project.  Present results at weekly group meetings.

Number of Slots: 2

Contact Information:
Bharat Bhuva
(615) 343-3184