Research Assistant Professor of Electrical Engineering
Radiation-Hardened Circuit Design,
Radiation-Enabled Compact Modeling, Simulation of Radiation Effects on Circuits
and Systems, Layout-Aware Modeling, Near-Threshold Computing, Digital Circuit
Design, Analog Circuit Design, Mixed-Signal Circuit Design
- J.S. Kauppila, D. R. Ball, M. L. Alles, R. D. Schrimpf, T. D. Loveless, J. A. Maharrey, R. C. Quinn, J. D. Rowe, L. W. Massengill, “Geometry-Aware Single-Event Enabled Compact Models for Sub-50nm Partially Depleted Silicon-on-Insulator Technologies,” IEEE Trans. Nucl. Sci., vol. 62, no. 4, pp. 1589-1598, Aug. 2015.
- J.S. Kauppila, T.D. Haeffner, D.R. Ball, A.V. Kauppila, T.D. Loveless, S. Jagannathan, A.L. Sternberg, B.L. Bhuva, L.W. Massengill, "Circuit-Level Layout-Aware Single-Event Sensitive-Area Analysis of 40-nm Bulk CMOS Flip-Flops Using Compact Modeling," IEEE Trans. Nucl. Sci., vol. 58, no. 6, pp. 2680-2686, Dec. 2011.
- J.S. Kauppila, A.L. Sternberg, M.L. Alles, A.M. Francis, J. Holmes, O.A. Amusan, L.W. Massengill, "A Bias-Dependent Single-Event Compact Model Implemented Into BSIM4 and a 90 nm CMOS Process Design Kit," IEEE Trans. Nucl. Sci., vol. 56, no. 6, pp. 3152-3157, Dec. 2009.
Jeffrey S. Kauppila received his Ph.D. in Electrical Engineering (2015), M.S. in Electrical Engineering (2003), and his B.E. in Electrical Engineering (2001) all from the Vanderbilt University. Dr. Kauppila's research activities are aligned with Vanderbilt University’s Institute for Space and Defense Electronics (ISDE), where he works in the area of radiation effects modeling and radiation hardened design for microelectronics. He joined ISDE in 2003 and his research focus has centered on the development of radiation-effects-enabled compact models, integration of models with existing and custom developed process-design-kits (PDK), and the application of the radiation-enabled models in the design of radiation-hardened strategic defense systems electronics. He is actively involved in the development and design of integrated circuits and test structures used to extract and calibrate electrical and radiation-enabled model parameters. Dr. Kauppila has analog/mixed signal design experience in bipolar junction transistor, bulk CMOS, silicon-on-insulator CMOS, and FinFET technologies with minimum process feature sizes from from 6um to 14nm. He has served as a reviewer for the IEEE Transactions on Nuclear Science and the Journal of Radiation Effects Research and Engineering several times. Dr. Kauppila has over 60 technical/trade publications on radiation-aware compact modeling, technology characterization for radiation effects response, and the effects of radiation on microelectronic circuit reliability. He has also written a chapter in the textbook Extreme Environment Electronics (ed. J.D. Cressler and H.A. Mantooth), presented an ITAR Tutorial presentation at the 2015 Hardened Electronics and Radiation Technology Society Technical Interchange Meeting, and presented a short course presentation entitled “Single-Event Modeling for Rad-Hard-by-Design Flows” at the 2016 IEEE Nuclear and Space Radiation Effects Conference. Dr. Kauppila is a licensed professional engineer in the state of Tennessee.